1. Field of the Invention
This invention relates to a CMOS semiconductor device, specifically to a protection against latch-up in a CMOS semiconductor device having a triple well structure.
2. Description of the Related Art
The CMOS semiconductor device having the triple well structure has been known to the industry. FIG. 4 is a cross-sectional view showing a structure of the CMOS semiconductor device having the triple well structure.
A reference numeral 20 denotes a P-type silicon substrate. A deep N-type well 21 is formed in a surface of the P-type silicon substrate 20. A P-type well 22 is formed in the deep N-type well 21. A shallow N-type well 23 is formed in a surface of the deep N-type well 21 and is disposed adjacent the P-type well 22. N+ regions 24 are formed in a peripheral surface of the deep N-type well 21. A power supply electric potential VDD is applied to the N+ regions 24.
An N-channel type MOS transistor Mn is formed on a surface of the P-type well 22 while a P-channel type MOS transistor Mp is formed on a surface of the shallow N-type well 23.
The N-channel type MOS transistor Mn is composed of a drain 27, a gate oxide film, a gate electrode 28 and a source 29 formed in or on the surface of the P-type well 22. P+ regions 25 are formed in the surface of the P-type well 22. The P+ regions 25 are connected to a ground electric potential VSS and set an electric potential of the P-type well 22 at the ground electric potential VSS.
The P-channel type MOS transistor Mp is composed of a source 30, a gate oxide film, a gate electrode 31 and a drain 32 formed in or on the surface of the deep N-type well 21. The N+ regions 26 are connected to the power supply electric potential VDD and set an electric potential of the shallow N-type well 23 at the power supply electric potential VDD.
The p-type well 22 and the shallow N-type well 23 are formed in the single deep N-type well 21 in the conventional CMOS semiconductor device having the triple well structure, as described above.
The conventional CMOS semiconductor device having the triple well structure is accompanied with a parasitic thyristor and has a problem that it is vulnerable to latch-up. The problem is described in detail hereafter.
A parasitic bipolar transistor Bip41 is formed between the shallow N-type well 23, the source 30 and the p-type well 22, as shown in FIG. 4. The shallow N-type well 23 makes a base, the source 30 makes an emitter and the p-type well 22 makes a collector of the PNP-type bipolar transistor Bip41.
Another parasitic bipolar transistor Bip42 is formed between the P-type well 22, the source 29 and the shallow N-type well 23. The P-type well 22 makes a base, the source 29 makes an emitter and the shallow N-type well 23 makes a collector of the NPN-type bipolar transistor Bip42.
Consequently, as shown in FIG. 5, the parasitic bipolar transistor Bip41 combined with the parasitic bipolar transistor Bip42 forms the parasitic thyristor which would cause latch-up. Thus, a base width WB1 of the bipolar transistor Bip41 and a base width WB2 of the bipolar transistor Bip42 have been enlarged in the conventional art as a countermeasure against the latch-up. When the base widths are enlarged, however, it takes larger area to layout the device.
This invention is directed to protecting the CMOS semiconductor device having the triple well structure against latch-up by preventing the parasitic thyristor from turning on while reducing the layout area of the device.